Xilinx puts the ARM hard core into the road map.
A Graphics Parallel Memory Organization Exploiting Request Correlations, in TC June 2010, shows an example of modeling memory partition and banking. The title is on graphics, but the method also applies to vision. This work shows that can be further improved on architectural template. The exploitation of request correlations can also be further improved.
The proceeding of CGO 2010 is available. Exciting moment. The conference is on April 24 – 28, 2010, but the proceeding is released before April 28. The ACM digital library is damn quick.
ODES: Workshop on Optimizations for DSP and Embedded Systems, co-located with CGO 2010, is also interesting. The program and proceeding of ODES 2010 is available from the workshop website.
Two papers in CGO 2010 are on the topic of tiling for autotuning:
- Parameterized tiling revisited, by Muthu Manikandan Baskaran from OSU, who has done good work on autuning for accelerator architecture.
- Automatic creation of tile size selection models, from IBM. The Tile-Size Selection (TSS) model is a nice example for modeling the system.
Some links for Prolog:
special issue MICPRO journal on exploitation of hardware accelerators, deadline on September 10, 2010.