2010-08-29 Log

Par4All, source-to-source transform targeting CUDA, openCL, etc. It uses the PIPS code transformation framework.

Domain-Specific Languages for Heterogeneous Computer Platforms, a talk by Pat Hanrahan.

Courses of SIGGRAPH 2010 available.

The program of PACT 2010 available.

Some benchmarking for CrossFire and SLI.

New version of CUVIlib was released. New functions are added.

Some interesting papers:

2010-08-04 Log

Proceeding of ISCAS 2010 available.

Visual Control of Robots Using Range Images, in Sensors 2010. A 3D time-of-flight (ToF) camera is used.

Some interesting papers from Computer Journal:

Drag-and-Drop vs. HDL?. It predicts, in a few years, people will not write HDL in practical projects.

2010-08-03 Log

Programmable Fabrics and Spatial Compilers (Loki), led by Robert Mullins in the computer architecture group of Cambridge.

Journal of Real-Time Image Processing has a special issue on improving display and rendering technologies for virtual environments:

Some recent papers in Journal of Real-Time Image Processing:

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines, in Sensors 2010.

FeedNetBack, a FP7 project on networked control systems.

2010-08-01 Log

dSPACE, hardware and software solutions for control.

Towards the classification of algorithmic skeletons, in 1996.

Factored Operating System (fos), OS support for parallel and heterogeneous architecture, from the carbon group.

Axel: a heterogeneous cluster with FPGAs and GPUs, from Wayne Luk’s group, in FPGA’10.

Quantifying Effective Memory Bandwidth of Platform FPGAs, in FCCM 2007.

External Memory Controller for Virtex II Pro, in ISSOC 2006.

HybridOS: runtime support for reconfigurable accelerators, in FPGA 2008.

A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines, in FCCM 2009. An SIMD friendly implementation of SVM.

Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips, in FPL 2007.

Efficient use of communications between an FPGA’s embedded processor and its reconfigurable logic, in FPGA’06.