The proceeding of PACT 2010 is released.

Some old news on Intel’s ISC 2010 press release. Die shot of Intel’s Aubrey Isle, included in the ‘Knights Ferry’ Intel Many Integrated Core (MIC). Slides for Intel’s ISC 2010 keynote has more info on the Knights Ferry.

Intel’s Sandy Bridge Architecture Exposed, from anandtech. The pin count is 1155, not the rumored 2011-pin. Say goodbye to the PCI-e between CPU and GPU. The CPU and GPU are now sharing the L3, which is reconfigurable to be cache or scratchpad memory. On the one hand, this improves the latency of CPU-GPU communication. On the other hand, the already scarce pin-bandwidth to DRAM will be even more scarce. To achieve higher graphics performance, it will need 2000 pins, unless Intel could stack the DRAM on chip.