A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management (doi), from KAIST, in Cool Chips 2012.
Review of ladar: a historic, yet emerging, sensor technology with rich phenomenology, in Journal of Optical Engineering (JOE) June 2012.
Image processing for three-dimensional scans generated by time-of-flight range cameras, in Journal of Electronic Imaging (JEI) May 2012.
Two survey papers in Journal of Imaging and Vision Computing June 2012:
An Overview of Static Pipelining, in Computer Architecture Letters Jan.-June 2012.
Considerations for Ultimate CMOS Scaling, by Kelin J. Kuhn with Intel, in IEEE Transactions on Electron Devices (TED) July 2012.
Performance of Industrial Communication Systems: Real Application Contexts, in Industrial Electronics Magazine (MIE) June 2012.
Some interesting articles in Solid-State Circuits Magazine June 2012:
Some interesting articles in Signal Processing Magazines June 2012:
Some interesting papers in ACM Transactions on Architecture and Code Optimization (TACO) June 2012:
Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures, from NXP, in ACM Transactions on Embedded Computing Systems (TECS) June 2012.
Robotica July 2012:
Proceedings of the 49th Annual Design Automation Conference (DAC 2012) is available in the ACM digital library.
Personal selection of some papers from DAC 2012:
- Accelerating neuromorphic vision algorithms for recognition
- SALSA: systematic logic synthesis of approximate circuits
- Architecture support for accelerator-rich CMPs, by Jason Cong, et al..
- Optimizing memory hierarchy allocation with loop transformations for high-level synthesis, by Jason Cong, et al.
- What to do about the end of Moore’s law, probably!
- Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications, from STMicroelectronics and CEA-LETI in Grenoble.
- Process variation in near-threshold wide SIMD architectures, from U. Mich and Arizona State U.
- Run-time power-down strategies for real-time SDRAM memory controllers, from TU Eindhoven and TU Delft.
- Near-threshold voltage (NTV) design: opportunities and challenges, from Intel.
- Near-threshold operation for power-efficient computing?: it depends…, from IBM.
- Assessing the performance limits of parallelized near-threshold computing, from U. Mich.
- Standard cell sizing for subthreshold operation, from TU Eindhoven.