Some recent work on saliency detection on FPGA:
2011-05-30 Log
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Tag Archives: fpga
Online Springer Books On Reconfigurable Computing and High Level Synthesis
- Dynamically Reconfigurable Systems — Architectures, Design Methods and Applications, edited by Marco Platzner, Jürgen Teich and Norbert Wehn, in 2010.
- Compilation Techniques for Reconfigurable Architectures , by João M.P. Cardoso and Pedro C. Diniz, in 2009.
- Reconfigurable Computing — Accelerating Computation with Field-Programmable Gate Arrays, edited by Maya Gokhale and Paul S. Graham, in 2005.
- Introduction to Reconfigurable Computing — Architectures, Algorithms, and Applications, edited by Christophe Bobda, in 2007.
- System Level Design of Reconfigurable Systems-on-Chip, edited by Nikolaos Voros and Konstantinos Masselos, in 2005.
- Processor Design — System-on-Chip Computing for ASICs and FPGAs, edited by Jari Nurmi, in 2007.
- Fine- and Coarse-Grain Reconfigurable Computing, edited by Stamatis Vassiliadis and Dimitrios Soudris, in 2007.
- Dynamic System Reconfiguration in Heterogeneous Platforms — The MORPHEUS Approach, edited by Nikolaos S. Voros, Alberto Rosti and Michael Hübner, in 2009.
- Dynamic Reconfigurable Architectures and Transparent Optimization Techniques — Automatic Acceleration of Software Execution, edited by Antonio Carlos Schneider Beck Fl. and Luigi Carro, in 2010.
- Run-time Adaptation for Reconfigurable Embedded Processors, edited by Lars Bauer and Jörg Henkel, in 2010.
- Multimedia Multiprocessor Systems — Analysis, Design and Management, by Akash Kumar, Henk Corporaal, Bart Mesman and Yajun Ha, in 2011.
- Design of Image Processing Embedded Systems Using Multidimensional Data Flow, by Joachim Keinert and Jürgen Teich, in 2011.
- Embedded System Design — Embedded Systems Foundations of Cyber-Physical Systems, by Peter Marwedel, in 2011.
- High-Level Synthesis — From Algorithm to Digital Circuit, edited by Philippe Coussy and Adam Morawiec, in 2008.
- Low-Power High-Level Synthesis for Nanoscale CMOS Circuits , edited by Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos and Priyadarsan Patra, in 2008.
- Higher-Level Hardware Synthesis , by Richard Sharp, in 2004.
- Co-design for System Acceleration — A Quantitative Approach, by Nadia Nedjah and Luiza De Macedo Mourelle, in 2007.
2011-05-02 Log
The new Eindhoven engineer, by Hans van Duijn, in April 2011.
Some random links to reconfigurable computing:
- Automatic generation of FPGA hardware accelerators using a domain specific language, in FPL 2009.
- Spatial Computation, by Mihai Budiu, et al., in ASPLOS 2004.
- Reconfigurable computing: architectures and design methods, a survey in 2005.
- Parallelizing applications into silicon, in FCCM 1999.
- A compiler approach to fast hardware design space exploration in FPGA-based systems, in PLDI 2002.
- Using estimates from behavioral synthesis tools in compiler-directed design space exploration, in DAC 2003.
- Achieving Programming Model Abstractions for Reconfigurable Computing, in TVLSI 2007.
- Performance and area modeling of complete FPGA designs in the presence of loop transformations, in TC 2004.
- Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system, in j.micpro 2004.
- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware , in Applied Reconfigurable Computing (ARC) 2007.
- Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations, in TCAD 2005.
- Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing , in 2011.
- Compile-time area estimation for LUT-based FPGAs, TODAES 2006.
- RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems, to appear in TECS.
- On estimations for compiling software to FPGA-based systems, by J. Cardoso, in ASAP 2005.
- Abstracting the Hardware/Software Boundary through a Standard System Support Layer and Architecture, PhD thesis of Erik Konrad Anderson, in 2007.
- Design Space Exploration Acceleration Through Operation Clustering, in TCAD 2010.
- Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques , by Pedro C. Diniz, in SAMOS 2004.
- Modeling Loop Unrolling: Approaches and Open Issues , by João M. P. Cardoso and Pedro C. Diniz, in SAMOS 2004.
- Sizing of processing arrays for fpga-based computation, in FPL 2006.
- Multilevel Granularity Parallelism Synthesis on FPGAs, extending the FCUDA, in FCCM 2011.
- Early Prediction of Hardware Complexity in HLL-to-HDL Translation, based on LLVM, in FPL 2010.
- High-level delay estimation technique for porting C-based applications on FPGA, in 2008.
Program locality analysis using reuse distance, in TOPLAS 2009.
IEEE Micro March/April 2011 is a special issue on Hot Chips 2010.
The IEEE Signal Processing Magazine May 2011 has some interesting articles on distributed image processing:
- Distributed Image Processing [From the Guest Editors]
- Distributed Camera Networks
- Distributed Computer Vision Algorithms
- Distributed and Decentralized Multicamera Tracking
- Multimedia Cloud Computing
Mathematical foundation of trace scheduling, in TOPLAS April 2011.
Closed-loop–based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study, in TECS April 2011.
Two interesting papers in Transactions on Mobile Computing:
- Breath: An Adaptive Protocol for Industrial Control Applications Using Wireless Sensor Networks, by researchers from KTH and Alberto Sagiovanni-Vincent.
- A Control-Theoretic Approach to Distributed Optimal Configuration of 802.11 WLANs, outperforming the heuristic approach.
Exploiting 162-Nanosecond End-to-End Communication Latency on Anton, from the research group of David E. Shaw, in SC 2010. It is surprising that the J-Machine and Cray T3E, both of which were implemented more than 15 years ago, are still on the top 10 list of the communication latency.
Retrospective: the J-machine, by William J. Dally, et al., in 25 years of the international symposia on Computer architecture (selected papers) 1998. What a machine.
Overcoming Communication Latency Barriers in Massively Parallel Scientific Computation, from the group of David E. Shaw, to appear in IEEE Micro.
Design and Evaluation of Multiple-Level Data Staging for Blue Gene Systems, in TPDS June 2011.
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors, from U Tokyo, in Transactions on Computers June 2011.
Silicon-Neuron Design: A Dynamical Systems Approach, in Circuits and Systems I May 2011.
Computing in Science and Engineering May-June 2011 is a special issue on Scientific Image Processing.
The proceeding of Virtual Reality Conference (VR) 2011 is available.
The proceeding of International Symposium on Virtual Reality Innovation (ISVRI) 2011 is available.
Real-Time Camera Pose Estimation for Wide-Area Augmented Reality Applications, in Computer Graphics and Applications May-June 2011.
Integrated Systems In The More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components, to appear in Design and Test of Computers. It paper extends the conference paper in VLSI Design 2010 with the same title.
FPGA-based implementation of high-speed active noise and vibration controllers, to appear in Control Engineering Practice.
IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators, to appear in j.micpro. (non-doi link)
Some random links to in-situ storage image sensor (ISIS):
- CMOS Image Sensors for High Speed Applications, in Sensors 2009. It devices an in-situ storage image sensor (ISIS) that can store 8 frames at the frame rate of one billion frames per second.
- CMOS Active-Pixel Sensor With In-Situ Memory for Ultrahigh-Speed Imaging, in IEEE Sensors Journal 2011. It can achieve 1.25 billion fps in theory, but is limited to 1 million fps due to illumination.
The PhD problem: are we giving out too many degrees?, yet another discussion on the over-supply of PhDs.