Software development and Integration in Robotics (SDIR VI), a workshop collocated with ICRA 2011. Some slides are available:

• Model-Driven Software Development for Robotics: An Overview, by Jan Broenink, Maarten Bezemer.
• Way of Working for Embedded Control Software Using Model-Driven Development Techniques, by Maarten Bezemer, Marcel Groothuis, Jan Broenink.

The cost of complexity in system identification: The Output Error casestar, open (doi), to appear in Automatica.

Multivariable predictive control for vibrating structures: An application (doi), to appear in Control Engineering Practice.

The proceeding of High-Performance Computer Architecture (HPCA) 2011 was released. Some interesting papers:

• Thread block compaction for efficient SIMT control flow , by Wilson W.L. Fung and Tor M. Aamodt.
• Data-triggered threads: Eliminating redundant computation , from the group of Dean Tullsen.
• A quantitative performance analysis model for GPU architectures , from the group of J. Owens.
• Calvin: Deterministic or not? Free will to choose , from Wisc.
• Dynamically Specialized Datapaths for energy efficient computing , from Wisc.
• Achieving uniform performance and maximizing throughput in the presence of heterogeneity , from the group of David Brooks.
• Fg-STP: Fine-Grain Single Thread Partitioning on Multicores , from Barcelona.
• Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors , from Wisc.
• Shared last-level TLBs for chip multiprocessors , from Rutgers.
• Fast thread migration via cache working set prediction , from the group of Dean Tullsen.
• Keynote address II: How’s the parallel computing revolution going? , from U. Texas.
• Efficient data streaming with on-chip accelerators: Opportunities and challenges , from IBM.
• Abstraction and microarchitecture scaling in early-stage power modeling , from IBM.

Some interesting papers in ISPASS 2011:

• Evaluation and optimization of multicore performance bottlenecks in supercomputing applications , from U. Texas.
• Memory access pattern-aware DRAM performance model for multi-core systems
• Characterizing multi-threaded applications based on shared-resource contention , from U. Virginia.
• A reconfigurable simulator for large-scale heterogeneous multicore architectures , by Jiayuan Meng and Kevin Skadron.
• Towards a scalable data center-level evaluation methodology
• A comparative benchmarking of the FFT on Fermi and Evergreen GPUs
• Where is the data? Why you cannot debate CPU vs. GPU performance without the answer , from U. Virginia.
• A comprehensive analysis and parallelization of an image retrieval algorithm
• Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation , from Wisc.
• Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware , from the group of Lieven Eeckhout in Ghent.
• WiLIS: Architectural modeling of wireless systems , from CSAIL MIT.
• Scalable, accurate multicore simulation in the 1000-core era , from MIT.